? semiconductor components industries, llc, 2001 july, 2001 rev. 3 1 publication order number: sg3525a/d sg3525a pulse width modulator control circuit the sg3525a pulse width modulator control circuit offers improved performance and lower external parts count when implemented for controlling all types of switching power supplies. the onchip +5.1 v reference is trimmed to 1% and the error amplifier has an input commonmode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors. a sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. a wide range of deadtime can be programmed by a single resistor connected between the c t and discharge pins. this device also features builtin softstart circuitry, requiring only an external timing capacitor. a shutdown pin controls both the softstart circuitry and the output stages, providing instantaneous turn off through the pwm latch with pulsed shutdown, as well as softstart recycle with longer shutdown commands. the under voltage lockout inhibits the outputs and the changing of the softstart capacitor when v cc is below nominal. the output stages are totempole design capable of sinking and sourcing in excess of 200 ma. the output stage of the sg3525a features nor logic resulting in a low output for an offstate. ? 8.0 v to 35 v operation ? 5.1 v 1.0% trimmed reference ? 100 hz to 400 khz oscillator range ? separate oscillator sync pin ? adjustable deadtime control ? input undervoltage lockout ? latching pwm to prevent multiple pulses ? pulsebypulse shutdown ? dual source/sink outputs: 400 ma peak figure 1. representative block diagram nor nor 16 15 12 4 3 6 5 7 9 1 2 8 10 reference regulator under- voltage lockout oscillator latch f/f q q - pwm error amp + - + - to internal circuitry v ref v ref v cc ground osc output sync rt ct discharge compensation inv. input noninv. input c soft-start shutdown 5.0k s r s 50 m a vc 13 output a 11 14 output b sg3525a output stage 5.0k device package shipping ordering information sg3525an pdip16 25 units/rail http://onsemi.com marking diagram a = assembly location wl = wafer lot yy = year ww = work week 1 16 pdip16 n suffix case 648 1 16 sg3525an awlyyww pin connections 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 (top view) inv. input sync osc. output r t discharge soft-start noninv. input c t compensation shutdown output a v c output b v cc v ref ground
sg3525a http://onsemi.com 2 maximum ratings (note 1) rating symbol value unit supply voltage v cc +40 vdc collector supply voltage v c +40 vdc logic inputs 0.3 to +5.5 v analog inputs 0.3 to v cc v output current, source or sink i o 500 ma reference output current i ref 50 ma oscillator charging current 5.0 ma power dissipation (plastic & ceramic package) t a = +25 c (note 2) t c = +25 c (note 3) p d 1000 2000 mw thermal resistance junctiontoair r q ja 100 c/w thermal resistance junctiontocase r q jc 60 c/w operating junction temperature t j +150 c storage temperature range t stg 55 to +125 c lead temperature (soldering, 10 seconds) t solder +300 c recommended operating conditions characteristics symbol min max unit supply voltage v cc 8.0 35 vdc collector supply voltage v c 4.5 35 vdc output sink/source current (steady state) (peak) i o 0 0 100 400 ma reference load current i ref 0 20 ma oscillator frequency range f osc 0.1 400 khz oscillator timing resistor r t 2.0 150 k w oscillator timing capacitor c t 0.001 0.2 m f deadtime resistor range r d 0 500 w operating ambient temperature range t a 0 +70 c 1. values beyond which damage may occur. 2. derate at 10 mw/ c for ambient temperatures above +50 c. 3. derate at 16 mw/ c for case temperatures above +25 c. application information shutdown options (see block diagram, front page) since both the compensation and softstart terminals (pins 9 and 8) have current source pullups, either can readily accept a pulldown signal which only has to sink a maximum of 100 m a to turn off the outputs. this is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. an alternate approach is the use of the shutdown circuitry of pin 10 which has been improved to enhance the available shutdown options. activating this circuit by applying a positive signal on pin 10 performs two functions: the pwm latch is immediately set providing the fastest turnoff signal to the outputs; and a 150 m a current sink begins to discharge the external softstart capacitor. if the shutdown command is short, the pwm signal is terminated without significant discharge of the softstart capacitor, thus, allowing, for example, a convenient implementation of pulsebypulse current limiting. holding pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turnon upon release. pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation.
sg3525a http://onsemi.com 3 electrical characteristics (v cc = +20 vdc, t a = t low to t high [note 4], unless otherwise noted.) characteristics symbol min typ max unit reference section reference output voltage (t j = +25 c) v ref 5.00 5.10 5.20 vdc line regulation (+8.0 v v cc +35 v) reg line 10 20 mv load regulation (0 ma i l 20 ma) reg load 20 50 mv temperature stability d v ref / d t 20 mv total output variation includes line and load regulation over temperature d v ref 4.95 5.25 vdc short circuit current (v ref = 0 v, t j = +25 c) i sc 80 100 ma output noise voltage (10 hz f 10 khz, t j = +25 c) v n 40 200 m v rms long term stability (t j = +125 c) (note 5) s 20 50 mv/khr oscillator section (note 6, unless otherwise noted.) initial accuracy (t j = +25 c) 2.0 6.0 % frequency stability with voltage (+8.0 v v cc +35 v) d f osc d vcc 1.0 2.0 % frequency stability with temperature d f osc d t 0.3 % minimum frequency (r t = 150 k w , c t = 0.2 m f) f min 50 hz maximum frequency (r t = 2.0 k w , c t = 1.0 nf) f max 400 khz current mirror (i rt = 2.0 ma) 1.7 2.0 2.2 ma clock amplitude 3.0 3.5 v clock width (t j = +25 c) 0.3 0.5 1.0 m s sync threshold 1.2 2.0 2.8 v sync input current (sync voltage = +3.5 v) 1.0 2.5 ma error amplifier section (v cm = +5.1 v) input offset voltage v io 2.0 10 mv input bias current i ib 1.0 10 m a input offset current i io 1.0 m a dc open loop gain (r l 10 m w ) a vol 60 75 db low level output voltage v ol 0.2 0.5 v high level output voltage v oh 3.8 5.6 v common mode rejection ratio (+1.5 v v cm +5.2 v) cmrr 60 75 db power supply rejection ratio (+8.0 v v cc +35 v) psrr 50 60 db pwm comparator section minimum duty cycle dc min 0 % maximum duty cycle dc max 45 49 % input threshold, zero duty cycle (note 6) v th 0.6 0.9 v input threshold, maximum duty cycle (note 6) v th 3.3 3.6 v input bias current i ib 0.05 1.0 m a 4. t low = 0 t high = +70 c 5. since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 6. tested at f osc = 40 khz (r t = 3.6 k w , c t = 0.01 m f, r d = 0 w ).
sg3525a http://onsemi.com 4 electrical characteristics (continued) characteristics symbol min typ max unit softstart section softstart current (v shutdown = 0 v) 25 50 80 m a softstart voltage (v shutdown = 2.0 v) 0.4 0.6 v shutdown input current (v shutdown = 2.5 v) 0.4 1.0 ma output drivers (each output, v cc = +20 v) output low level (i sink = 20 ma) (i sink = 100 ma) v ol 0.2 1.0 0.4 2.0 v output high level (i source = 20 ma) (i source = 100 ma) v oh 18 17 19 18 v under voltage lockout (v8 and v9 = high) v ul 6.0 7.0 8.0 v collector leakage, v c = +35 v (note 7) i c(leak) 200 m a rise time (c l = 1.0 nf, t j = 25 c) t r 100 600 ns fall time (c l = 1.0 nf, t j = 25 c) t f 50 300 ns shutdown delay (v ds = +3.0 v, c s = 0, t j = +25 c) t ds 0.2 0.5 m s supply current (v cc = +35 v) i cc 14 20 ma 7. applies to sg3525a only, due to polarity of output pulses. reference regulator flip/ flop pwm - + e/a dut v ref clock 16 4 0.1 3 6 7 5 deadtime 100 w 0.001 comp 10k 9 0.01 1 2 1 2 3 1 2 3 3 2 1 3 + - 1 = v io 2 = 1(+) 3 = 1(-) 0.1 0.009 1.5k 1.0k 3.0k pwm adj. sync rt ramp 50 m a 5.0k 5.0k 15 13 11 v c out a 0.1 0.1 1.0k, 1.0w (2) 14 out b gnd 12 8 softstart 5.0 m f 10 2.0k shutdown v ref + o s c i l l a t o r v/i meter v cc a 1 2 b figure 2. lab test fixture
sg3525a http://onsemi.com 5 r t w , timing resistor (k ) figure 3. oscillator charge time versus r t figure 4. oscillator discharge time versus r d figure 5. error amplifier open loop frequency response figure 6. output saturation characteristics 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000 charge time ( m s) 6 57 r d * c t r t * r d = 0 w 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 discharge time ( m s) , dead time resistor () d w r 1.0 10 100 1.0 k 10 k 100 k 1.0 m 10 m 1 2 9 c p r z f, frequency (hz) , voltage gain (db) vol - + a r z = 20 k v ref r t c t sync discharge gnd 16 6 5 3 7 12 q2 q1 q6 q9 2.0k 2.0k 14k q10 q11 5.0pf 400 m a 23k q4 q7 1.0k q12 q13 3.0k 250 4 blanking to output ramp to pwm q14 25k 7.4k q5 q8 q3 osc output 1.0k 15 q3 v cc 9 30 compensation 1 2 q4 q1 q2 inverting input 5.8v 100 m a to pwm comparator 200 m a noninverting input figure 7. oscillator schematic 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 i o, output source or sink current (a) , saturation voltage (v) sat v sink sat, (v ol ) source sat, (v c -v oh ) v cc = +20 v t j = +25 c figure 8. error amplifier schematic 200 100 50 20 10 5.0 2.0 500 400 300 200 100 0 100 80 60 40 20 0 -20 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
sg3525a http://onsemi.com 6 figure 9. output circuit (1/2 circuit shown) figure 10. singleended supply figure 11. pushpull configuration figure 12. driving power fets low power transformers can be driven directly by the sg3525a. automatic reset occurs during deadtime, when both ends of the primary winding are switched to ground. q1 r1 r2 13 to output filter 11 14 12 v c sg3525a a b gnd + v supply for single-ended supplies, the driver outputs are grounded. the v c terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. in conventional push-pull bipolar designs, forward base drive is controlled by r1-r3. rapid turn-off times for the power devices are achieved with speed-up capacitors c1 and c2. v c sg3525a a b gnd +v supply r1 13 12 11 14 r3 c2 c1 q1 q2 t1 r2 the low source impedance of the output drivers provides rapid charging of power fet input capacitance while minimizing external components. + v supply v c sg3525a a b gnd 11 14 q1 q2 t1 r1 13 12 v c sg3525a a b gnd 13 11 14 12 +v supply t1 q1 q2 r2 r1 t2 c1 c2 figure 13. driving transformers in a halfbridge configuration q3 v cc q5 q4 q7 q9 q10 13 v c v ref q1 q2 q6 omitted in sg3527a 5.0k 10k 10k 2.0k q11 q6 q8 5.0k 11, 14 output clock f/f pwm
sg3525a http://onsemi.com 7 package dimensions pdip16 n suffix case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
sg3525a http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. sg3525a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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